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E2B0033-27-Y2 Semiconductor
Semiconductor MSM6262-XX
This version:MSM6262-XX Nov. 1997 Previous version: Mar. 1996
DOT MATRIX LCD CONTROLLER WITH 48-DOT COMMON DRIVER
GENERAL DESCRIPTION
The MSM6262-XX is a dot matrix LCD controller which is fabricated by OKI's low power consumption CMOS silicon gate technology. In combination with 8-bit microcontroller, the MSM6262-XX can control the dot matrix character type LCD module. The MSM6262-XX is provided with a serial data transfer output. So, a maximum of 160 characters can be controlled by combining this device with the MSM5259, MSM5839C, or MSM5260. The MSM6262-XX is recommended for use in an LCD panel which is capable of displaying 81 to 160 characters. If an LCD panel of which display capacity is 80 characters or less is used, the MSM6222B-xx is recommended. The MSM6262-XX is best suited to be used as an LCD controller for applications such as electronic typewriters, POS system terminals, and data banks.
FEATURES
* Dot matrix LCD controller/driver for three different font configuration (5 x 7 dots, 5 x 11 dots and 5 x 12 dots) * Up to 160 characters can be controlled (Display data RAM ... 160 x 9-bit) * On-chip character generator ROM (CGROM) for 256 different characters 5 x 7 dots ... 128 characters 5 x 11 dots ... 96 characters 5 x 12 dots ... 32 characters * On-chip character generator RAM (CGRAM) (32 x 8-bit) 5 x 8 dots ... 4 kinds 5 x 12 dots ... 2 kinds * Easy interface with Z80, 6809, 80C49, and 80C51 * Underline function * Shift function for g, i, p, q and y * Selectable driving duty
Duty 1/16 1/24 1/32 1/48 Font Configuration (dots) 5x 7 5 x 11 5x 7 5 x 11 Cursor Display Available Available Available Available Display (characters x lines) 80 x 2 80 x 2 40 x 4 40 x 4
* Package : 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM6262-XXGS-BK) xx indicates code number.
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8
Address counter (ADC) Timing generator
BLOCK DIAGRAM
VDD VSS OSC1 OSC2 OSC3
Semiconductor
8
CP LOAD DF
8
RESET
Instruction 9 register (I/R)
Instruction decoder
9
Display data RAM (DDRAM) 160 x 9 bits
68 series/80 series CS R/W (WR) E (RD) A0 A1
Input/ Output buffer
6
8 9 8 8 1 5 9
48-bit shift register COMMON signal driver
8
Data register (DR) Character generator ROM (CGROM), 11,680 bits
8
DB0 - DB7
48
48
COM1 - COM48
TEST1 TEST2 TEST3 Busy flag
2
Character generator RAM (CGRAM), 256 bits
Cursor blink, under-line function control
5 5
1
DO
LCD driving voltage
V1 V4 V5
Parallel / Serial converter
2
BUSY1 OUT BUSY2 OUT
MSM6262-XX
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Semiconductor
MSM6262-XX
INPUT AND OUTPUT CONFIGURATION
Input pin
VDD
To the inside of the device Applicable pins: OSC1, 68 series/80 series, CS R/W (WR), E (RD) A0, A1 VDD VDD
To the inside of the device
Applicable pin: RESET
Input /Output pin
VDD
VDD
From the inside of the device
To the inside of the device
Applicable pins: OSC2, OSC3 VDD VDD
To the inside of of the device VDD
From the inside of the device
Applicable pins: DB0 - DB7
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MSM6262-XX
Output pin
From the inside of the device Applicable pins: CP, LOAD, DF, DO, BUSY1 OUT, BUSY2 OUT
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Semiconductor
MSM6262-XX
PIN CONFIGURATION (TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
COM 46 COM 47 COM 48 VSS (GND) OSC1 OSC2 OSC3 TEST1 TEST2 TEST3 RESET 68 series/80 series CS E (RD) R/W (WR) A0 A1 DB0 DB1 DB2 DB3 DB4 DB5 DB6
65
COM 45 COM 44 COM 43 COM 42 COM 41 COM 40 COM 39 COM 38 COM 37 COM 36 COM 35 COM 34 COM 33 COM 32 COM 31 COM 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
COM 29 COM 28 COM 27 COM 26 COM 25 COM 24 COM 23 COM 22 COM 21 COM 20 COM 19 COM 18 COM 17 COM 16 COM 15 COM 14 COM 13 COM 12 COM 11 COM 10 COM 9 COM 8 COM 7 COM 6
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
DB7 BUSY 1 OUT BUSY 2 OUT DF LOAD CP DO VDD V1 V4 V5 COM 1 COM 2 COM 3 COM 4 COM 5
80-Pin Plastic QFP
40
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Semiconductor
MSM6262-XX
PIN DESCRIPTIONS
Symbol OSC1 OSC2, OSC3 RESET 68 series/80 series CS R/W (WR) Type I/O I I I I Description Clock oscillating pins required for internal operation upon receipt of the LCD drive signal and CPU instruction. Reset pin Selection pin for either 68 series CPU or 80 series CPU Chip select pin. By setting CS at "L" level, MSM6262-XX is set at selecting condition. R/W pin of 68 series CPU shall be connected to this pin, while WR pin shall be connected to this pin in the case of 80 series CPU. E (RD) I E pin of 68 series CPU shall be connected to this pin, while RD pin shall be connected to this pin in the case of 80 series CPU. A0, A1 DB0 - DB7 I I/O The address bus of CPU shall be connected to these pins. Instruction code is set by these pins. The data bus of CPU shall be connected to these pins. These pins are used to set the data of the instruction or to read the data. TEST1 - TEST3 VDD, VSS V1, V4, V5 DO CP I -- -- O O Test pins. Normally these pins should be set at VSS or open. Voltage supply pins. VDD is also used for the common bias voltage level to drive the LCD. Common bias voltage input pins to drive the LCD Serial data output pin for SEGMENT drivers Clock pulse output pin. The clock output from this pin enables the character pattern data, which is output from DO, to input to the SEGMENT drivers (MSM5839C or MSM5259). LOAD O Load signal output pin. The character pattern data to the SEGMENT drivers, which was output from DO and CP, is loaded to the LCD output of the SEGMENT drivers, synchronized with the COMMON signal. DF COM1 - COM48 BUSY1 OUT O O O B-type AC signal output pin to drive the LCD COMMON signal output pins to drive the LCD This pin shows the internal condition of MSM6262-XX. "H" shows that MSM6262-XX is in internal operation, while "L" shows that MSM6262-XX is ready to receive the instruction from the CPU. BUSY2 OUT O This pin shows that MSM6262-XX is in internal operation based on the instruction from the CPU, or MSM6262-XX is in display revising operation based on the instruction from the CPU. "H" shows that MSM6262-XX is in internal operation, while "L" shows that the display on the LCD has been established and the MSM6262-XX is ready to receive an instruction.
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Semiconductor
MSM6262-XX
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Supply Voltage for Driving LCD Symbol VDD V1, V4, V5 Condition Ta = 25C, VDD-VSS Ta = 25C Rating -0.3 to +7.0 VDD - 12 to VDD + 0.3 Unit V V Applicable Pin VDD, VSS V1, V4, V5
OSC1, RESET Input Voltage VIN Ta = 25C -0.3 to VDD + 0.3 V 68 series / 80 series CS, A0, A1, R/W (WR) E (RD), DB0 - DB7
Power Dissipation Storage Temperature
PD TSTG
Ta = 25C --
500 -55 to +125
mW C
-- --
RECOMMENDED OPERATING CONDITOINS
Parameter Supply Voltage LCD Driving Voltage Operating Temperature Symbol VDD VLCD Top Condition -- 1/5 bias, VDD-V5
1/6, 1/7 bias, VDD-V5
Range 4.5 to 5.5 3.0 to 11 4.0 to 11 4.5 to 11 -20 to +75
Unit V V V V C
Applicable Pin VDD, GND VDD, V1, V4, V5 --
1/8 bias, VDD-V5 -- Note: For bias, refer to *3 in the section "DC Characteristics".
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MSM6262-XX
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter "H" Input Voltage "L" Input Voltage "H" Output Voltage "L" Output Voltage "H" Input Voltage "L" Input Voltage "H" Output Voltage "L" Output Voltage "H" Output Voltage "L" Output Voltage "H" Output Voltage "L" Output Voltage COM Voltage Drop "H" Input Current "L" Input Current Symbol VIH1 VIL1 VOH1 VOL1 VIH2 VIL2 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VCOM IILH1 IILL1 IDD1 Supply Current IDD2 Condition -- -- IO = -250 mA IO = 1.8 mA -- -- IO = -500 mA IO = 500 mA IO = -1 mA IO = 1 mA IO = -100 mA IO = 1.6 mA IO = 50 mA VIN = VDD VIN = VSS *2 VDD = 5 V, fOSC = 500 kHz (RC oscillation) VDD = 5 V, *2 fIN = 500 kHz (external oscillation) *3 LCD Driving Voltage "H" Input Current "L" Input Current VLCD VDD-V5 1/5 bias 1/6-1/7 bias 1/8 bias IILH2 IILL2 VIN = VDD VIN = VSS,VDD = 5 V *1 Min. 2.2 -0.3 2.4 -- VDD-0.8 -0.3 0.85 VDD -- 0.85 VDD -- 2.4 -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (VDD = 4.5 to 5.5 V , Ta = -20 to +75C) Max. VDD 0.7 -- 0.4 VDD 0.8 -- 0.15 VDD -- 0.15 VDD -- 0.4 2.9 1 -1 1.5 Unit V V V V V V V V V V V V V mA mA mA VDD -- 3.0 4.0 4.5 -- -8 -- -- -- -- -- -20 1.5 11 11 11 2 -60 mA V V V mA mA RESET V1 , V4, V5 CP BUSY1 OUT BUSY2 OUT COM1 - COM48 CS, R/W (WR) E (RD), A0, A1 OSC1, 68series/ 80series Applicable Pin CS, R/W (WR) E (RD), A0, A1 DB0 - DB7 DB0 - DB7 OSC1, RESET 68series/80series DO, LOAD, DF
*1.
*2. *3.
This is applicable to the voltage drop which is caused between VDD, V1, V4, V5 and COM1 - COM48 when a current of 50 mA is flowed in/out to/from all of COM1 - COM48. (When the output level is either VDD or V1, it should be applied only when the current flows in. When the output level is either V4 or V5, it should be applied only when the current flows in. In this case, +5V is applied to VDD and V1, while -6 V is applied to V4 and V5.) This is applicable to the current which flows in to VDD under following conditions. VDD = 5 V, VSS = 0 V, V1 = 2.8 V, V4 = -3.8 V, V5 = -6 V, No load, No interface with CPU V1 to V5 should be set at as follows.
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Semiconductor
MSM6262-XX
Pin
Font config u
No. of lines (N)
ration
2 lines 5x8 1 VDD - -- VLCD 5 4 VDD - -- VLCD 5 VDD - VLCD 5 x 12 1 VDD - -- VLCD 6 5 VDD - -- VLCD 6 VDD - VLCD 5x8 1 VDD - -- VLCD 7 6 VDD - -- VLCD 7 VDD - VLCD
4 lines 5 x 12 1 VDD - -- VLCD 8 7 VDD - -- VLCD 8 VDD - VLCD
V1 V4 V5
VLCD = LCD driving voltage
AC Characteristics
Parameter Input Frequency Input Clock Duty Input Clock Rise Time Input Clock Fall Time RC Oscillation Frequency "H" Input Current "L" Input Current Symbol fIN fDUTY tr tf fCR IILH3 IILL3 VIN = VDD VIN = VSS VDD = 5 V Condition *1, *2 *2 *2 *2 *3 Min. 300 45 -- -- 300 -- -45 Typ. 500 50 -- -- 500 -- -120
(VDD = 4.5 to 5.5V , Ta = -20 to +75C) Max. 700 55 100 100 700 1 -250 Unit kHz % ns ns kHz mA mA DB0 - DB7 OSC1, OSC2, OSC3 OSC1 Applicable Pin
*1
Open
OSC3
*3
OSC3 Rf = 39 kW 5% Cf = 22 pF 10% (Keep the wiring from OSC1, OSC2, and OSC3 to Rf and Cf as short as possible.)
Open
OSC2
Rf Cf
OSC2
Oscillation source
OSC1
OSC1
*2
TH VDD-0.8 V 0.5 VDD 0.8 V tr VDD-0.8 V 0.5 VDD 0.8 V 0.5 VDD TL
tf TH fDUTY = ------- x 100% TH + TL
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MSM6262-XX
TIMING DIAGRAM
Interface with 80 Series CPU
(VDD = 4.5 to 5.5V, Ta = -20 to +75C) Parameter Address Set-up Time CS Set-up Time WR "L" Pulse Width RD "L" Pulse Width WR, RD "H" Pulse Width Address Hold Time CS Hold Time Data Set-up Time Data Hold Time (Write operation) WR, RD Fall Time WR, RD Rise Time Data Delay Time Data Hold Time (Read operation) Busy Output Delay Time Symbol tSA1 tSA2 tWWR tWRD tWH tHA1 tHA2 tSWD tHWD tf tr tSRD tHRD tBD Min. 110 100 320 320 210 25 25 300 20 -- -- -- 0 -- Max. -- -- -- -- -- -- -- -- -- 25 25 190 -- 410 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Semiconductor
MSM6262-XX
Write operation
A0,A1
VIH VIL tSA1
VIH VIL tHA1
CS VIL tSA2 R/W (WR) VIH VIL tf tSWD DB0 - DB7 VIH VIL Valid data tr tHWD VIH VIL tBD BUSY 1 OUT, BUSY 2 OUT VOH tW WR tHA2 tWH VIH VIL VIH VIL
Read operation
A0,A1
VIH VIL tSA1
VIH VIL tHA1
CS VIL tSA2 E (RD) VIH VIL tf tSRD DB0 - DB7 VOH VOL tWRD tHA2 tWH VIH VIL tr tHRD Valid data VOH VOL VIH VIL
Refer to the DC Characteristics for the definition of VIH, VIL, VOH and VOL.
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Semiconductor
MSM6262-XX
* Interface with Z80
Z80 VSS RD WR IORQ A0 - A15 * * * Address Decoder * * DB0 - DB7 CS A0, A1 DB0 - DB7 MSM6262-XX 68 series/80 series E (RD) R/W (WR)
* A pull-up resistor of about 50 kW is required when the output of CPU becomes high impedance.
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Semiconductor
MSM6262-XX
* Interface with 80C49
MSM80C49 VSS RD WR ALE DB0 - DB7 STB 8282 Address Decoder * * CS A0, A1 DB0 - DB7
* A pull-up resistor of about 50 kW is required when the output of CPU becomes high impedance.
MSM6262-XX 68 series/80 series E (RD) R/W (WR)
* *
P20 - P22
* Interface with 80C51
MSM80C51 VSS RD WR ALE P00 - P07 STB 8282 Address Decoder * * CS A0, A1 DB0 - DB7
* A pull-up resistor of about 50 kW is required when the output of CPU becomes high impedance.
MSM6262-XX 68 series/80 series E (RD) R/W (WR)
* *
P20 - P22
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Semiconductor Interface with 68 Series CPU
MSM6262-XX
(VDD = 4.5 to 5.5 V, Ta = -20 to +75C) Parameter Cycle Time Address, R/W Set-up Time CS Set-up Time E signal "H" Pulse Width E signal "L" Pulse Width Address, R/W Hold Time CS Hold Time Data Set-up Time Data Hold Time (Write operation) E signal Rise Time E signal Fall Time Data Delay Time Data Hold Time (Read operation) Busy Output Delay Time Symbol tC tB1 tB2 tW tL tA1 tA2 tI tH tr tf tD tO tBD Min. 500 100 90 220 210 20 20 225 30 -- -- -- 10 -- Max. -- -- -- -- -- -- -- -- -- 25 25 180 -- 410 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Semiconductor
MSM6262-XX
Write operation
A0, A1
VIH VIL tB1
VIH VIL tA1 VIL tW VIH tL VIH VIL tI VIH VIL tB2 tC tf tH VIH VIL VIL
R/W (WR)
VIL
E (RD)
VIL tr
DB0 - DB7
Valid data tA2
CS VIL tBD Busy 1 OUT, Busy 2 OUT VOH VIL
Read operation
A0, A1
VIH VIL tB1
VIH VIL tA1 VIH tW VIH tL VIH VIL tD VOH VOL tB2 tC tf tO VOH VOL VIL
R/W (WR)
VIH
E (RD)
VIL tr
DB0 - DB7
Valid data tA2
CS VIL VIL
Refer to the DC Characteristics for the definition of VIH, VIL, VOH, and VOL.
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MSM6262-XX
* Interface with 6809
6809 O E R/W A0 - A15 Address decoder VDD * * * * DB0 - DB7 MSM6262-XX 68 series/80 series E (RD) R/W(WR) CS A0, A1 DB0 - DB7
* A pull-up resistor of about 50 kW is required when the output of CPU becomes high impedance.
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Semiconductor Interface with Segment Driver
MSM6262-XX
(VDD = 4.5 to 5.5 V, Ta = -20 to +75C, fOSC = 500 kHz) Parameter Clock "L" Pulse Width Clock "H" Pulse Width Do Set-up Time Do Hold Time LOAD, Clock Set-up Time LOAD, Clock Hold Time LOAD, "H" Pulse Width DF Delay Time Symbol tLW(CP) tHW(CP) tSETUP tHOLD tCL tLC tHW(L) tM Min. 400 400 200 200 200 100 400 -500 Max. -- -- -- -- -- -- -- 500 Unit ns ns ns ns ns ns ns ns
DO
VOH VOL tSETUP VOH VOH
VOH VOL tHOLD VOH tCL VOH tHW(L) tM VOH VOL tLC VOL
CP
VOL
VOL
tLW(CP) LOAD
THW(CP) VOH
DF
Refer to the DC Characteristics for the definition of VIH, VIL, VOH, and VOL.
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Semiconductor Reset Waveform
MSM6262-XX
(VDD = 4.5 to 5.5 V, Ta = -20 to +75C) Parameter "L" Input Time upon power on "L" Input Width when in operation Rise Time Symbol tRR1 tRLW tRR2 Min. 0.25 0.5 0.1 Max. -- -- 200 Unit ms ms ms
4.5 V
VDD tRR1
0V tRR2 VIH tRR2 VIH VIL tRLW VIL
RESET
VIL
Refer to the DC Characteristics for the definition of VIH, VIL, VOH, and VOL.
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MSM6262-XX
FUNCTIONAL DESCRIPTION
1. Instruction Register (IR) and Data Register (DR) The MSM6262-XX has two registers, instruction register (IR) and data register (DR). IR is used to store the address code or instruction code of display data RAM (DD RAM) or character generator RAM (CG RAM). This register can be written by the CPU, but cannot be read out by the CPU. DR is used to store the data to write into (or read out) the data to/from DD RAM or CG RAM. The data written into DR by the CPU is automatically written into the DD RAM or CG RAM. When an address code is written into IR, the data of the specified address is automatically transferred to the DR from either DD RAM or CG RAM. By having the CPU subsequently read the DR, it is possible to verify DD RAM or CG RAM data. After the writing of DR by the CPU, the DD RAM or CG RAM of the next address is selected to be ready for the next CPU writing. Likewise, after the reading operation of the CPU, DD RAM or CG RAM data of the next address is transferred to the DR, when CPU is ready for the next reading operation. 2. Busy Flag (BF) When the output of BUSY 1 OUT is "H", MSM6262-XX is engaged in internal operation. When the output of BUSY 2 OUT is "H", it indicates that MSM6262-XX is engaged in internal operation or MSM6262-XX is engaged in the revising of the display starting line on the LCD. (Refer to the instruction table.) When the output of BUSY 1 OUT is "H", any input of new instruction is ignored. So, before setting a new instruction, it is necessary to check whether BUSY 1 OUT and BUSY 2 OUT are at "L". 3. Address Counter (ADC) The address counter (ADC) allocates the address for the DD RAM and CG RAM write/read and also for the cursor display. When the instruction code for a DD RAM address or CG RAM address setting is input to IR, after deciding whether it is DD RAM or CG RAM, the address counter code is transferred from IR to ADC. After writing (reading) the display data to (from) the DD RAM or CG RAM, the ADC increments (or decrements) by 1 automatically as its internal operation.
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Semiconductor 4. Timing Generator Circuit
MSM6262-XX
This circuit generates the timing signal for the internal operation by CPU's instruction as well as to operate the internal circuit of DD RAM, CG RAM, CG ROM and so forth. It also generates the transfer signal to the SEGMENT driver (MSM5839C or MSM5259). The internal operation accessed by the CPU and internal operation for LCD display is independent. So, a manipulation such as writing data from CPU to DD RAM will not have an influence such as display flickering upon any part other than the display part to which the data is written. 5. Display Data RAM (DD RAM) DD RAM is used to store the 8-bit character code (refer to Table 1) and 1-bit under-line data. The address of DD RAM corresponds to the display position on the LCD. The correspondence is described below. DD RAM address (set to ADC) is described as hexadecimal.
DB7 ADC MSB Hexadecimal Hexadecimal DB6 DB5 DB4 DB3 DB2 DB1 DB0 LSB
Example: When DD RAM address is 3A L L 3 H H H L A H L
(1) Relation between DD RAM and display position in 2-line display mode
Digit 1 1st line 2nd line 00 80
2 01 81
3 02 82
4 03 83
5 04 84
--- --- ---
79 4E CE
80 4F CF
Display position DD RAM address (hexadecimal)
Note: The address of the last digit of the first line and the first digit of the second line does not have any continuity.
(2) When 2 pieces of MSM5389C(or MSM5259) are connected to MSM6262-XX, 32 characters can be displayed from the first digit to yhe 16th degit.
Digit 1 23 00 01 02 80 81 82
1st line 2nd line
4 5 03 04 83 84
6 7 05 06 85 86
89 07 08 87 88
10 11 12 13 14 15 16 09 0A 0B 0C 0D 0E 0F 89 8A 8B 8C 8D 8E MSM5839C (2) MSM5259 (2) } 8F
{ or
MSM5839C (1) MSM5259 (1)
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MSM6262-XX
When the display is shifted by an instruction, the relation between the DD RAM address and the display position becomes as follows.
(Shift to the right) Digit 1 2 4F 00 CF 80 3 01 81 4 02 82 5 03 83 6 04 84 7 05 85 89 06 07 86 87 10 11 08 09 88 89 12 13 14 15 16 0A 0B 0C 0D 0E 8A 8B 8C 8D 8E
1st line 2nd line
{ or 1st line 2nd line 01 81 02 82
MSM5839C (1) MSM5259 (1) 03 83 04 84 05 85 06 86 07 87 08 09 88 89
MSM5839C (2) MSM5259 (2) } 0A 0B 0C 0D 0E 8A 8B 8C 8D 8E 0F 8F 10 90
(Shift to the left)
(3) The maximum DD RAM capacity of MSM6262-XX is for 160 characters. So, up to 10 pieces of MSM5839C (or MSM5259) can be connected in the case of 2-line display mode.
Digit 1 1st line 2nd line 00 80 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 11 91 --- --- --- 73 74 48 75 76 77 78 79 80 4F
01 02 81 82
03 04 83 84
05 06 85 86
07 08 87 88
09 0A 0B 0C 0D 0E 89 8A 8B 8C 8D 8E MSM5839C (2) MSM5259 (2)
0F 10 8F 90
49 4A 4B 4C 4D 4E
C8 C9 CA CB CC CD CE CF MSM5839C (10) MSM5259 (10) }
{ or
MSM5839C (1) MSM5259 (1)
MSM5839C (3)-(9) MSM5259 (3)-(9)
(4) Relation between the DD RAM and display position in 4-line display mode
Digit 1 1st line 2nd line 3rd line 4th line 00 40 80 C0 2 01 41 81 C1 3 02 42 82 C2 4 03 43 83 C3 5 04 44 84 C4 --- --- --- --- --- 39 26 66 A6 E6 40 27 67 A7 E7 DD RAM address (hexadecimal) Display position
Note: The address of the last digit of the previous line and the first digit of the next line does not have any continuity.
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MSM6262-XX
(5) When 2 pieces of MSM5839C (or MSM5259) are connected to MSM6262-XX, 64 characters can be displayed from the first digit to the 16th digit.
Digit 1 23 1st line 00 01 02 2nd line 40 41 42 3rd line 80 81 82 4th line 4 5 03 04 43 44 83 84 6 7 05 06 45 46 85 86 89 07 08 47 48 87 88 10 11 12 13 14 15 16 09 0A 0B 0C 0D 0E 0F 49 4A 4B 4C 4D 4E 89 8A 8B 8C 8D 8E 4F 8F
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CB CF { or MSM5839C (1) MSM5259 (1) MSM5839C (2) MSM5259 (2) }
When the display is shifted by an instruction, the relation between the DD RAM address and the display position becomes as follows.
(shift to right direction) Digit 1 23 4 5 1st line 27 00 01 02 03 2nd line 67 40 41 42 43 3rd line 4th line A7 80 E7 { or 1st line 2nd line 3rd line 4th line 01 41 81 02 42 82 81 82 83
6 04 44 84
7 05 45
89 06 07 46 47 87
10 11 08 09 48 88 49 89
12 13 14 15 16 0A 0B 0C 0D 0E 4A 4B 4C 4D 4E 8A 8B 8C 8D 8E
85 86
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE MSM5839C (1) MSM5259 (1) 03 43 83 04 44 84 05 45 85 06 46 07 47 08 09 48 49 88 89 MSM5839C (2) MSM5259 (2) } 0A 0B 0C 0D 0E 0F 4A 4B 4C 4D 4E 4F 8A 8B 8C 8D 8E 8F 10 50 90 D0
86 87
C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF (shift to left direction)
(6) The maximum DD RAM capacity of MSM6262-XX is for 160 characters. So, up to 5pieces of MSM5839C (or MSM5259) can be connected in the case of 4-line display mode.
Digit 1 1st line 2nd line 3rd line 4th line 00 40 80 C0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 10 50 90 11 51 91 --- --- --- --- --- 33 34 35 36 37 38 39 40
01 02 03 04 41 42 43 44 81 82 83 84 C1 C2 C3 C4
05 06 45 46 85 86 C5 C6
07 08 09 0A 0B 0C 0D 0E 0F 47 48 49 4A 4B 4C 4D 4E 4F 87 88 89 8A 8B 8C 8D 8E 8F
20 21 22 23 24 25 26 27 60 61 62 63 64 65 66 67 A0 A1 A2 A3 A4 A5 A6 A7 E0 E1 E2 E3 E4 E5 E6 E7
C7 C8 C9 CA CB CC CD CE CF D0 D1
or
MSM5839C (1) MSM5259 (1)
MSM5839C (2) MSM5259 (2)
MSM5839C (3),(4) MSM5259 (3),(4)
MSM5839C (5) MSM5259 (5)
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Semiconductor
MSM6262-XX
6. Cursor/Blink Control Circuit This is the circuit to control the generation of cursor and its blinking. This circuit is controlled by the program of the CPU. The position of the cursor and its blink appears on the position according to the ADC contents, which correspond to the address of DD RAM. For example, when the ADC is set as "07" (hex.), the position of cursor and its blinking becomes as follows.
DB7 ADC 0 0 0 2-line display Digit 12 00 01 80 81 4-line display Digit 12 00 01 40 41 80 81 0 --- 0 0 1 7 Cursor and its blinking position 3 02 82 4 5 6 05 85 7 8 9 08 88 --- --- 79 80 1 DB0 1
03 04 83 84
06 -- 07 86 87
4E 4F CE CF
Cursor and its blinking position 3 02 42 82 4 5 6 05 7 8 9 --- --- --- --- 39 40 26 27 66 67
03 04 43 44 83 84
45 46 85 86
06 -- 08 07 47 48 87 88
A6 A7 --- C0 C1 C2 C3 C4 C5 C6 C7 C8 E6 E7 Note: Cursor display and blinking can be performed even when the CG RAM address is set in the ADC. So, it is necessary to disable the cursor display and blinking when the CG RAM address is set in the ADC.
7. Underline Control Circuit First, either underline display mode or underline blinking mode has to be set by the CPU. When an instruction to enable the underline function is input from the CPU, the cursor display shifts to the right direction (increment) or left direction (decrement). Display of underline appears (or disappears) on the same position where cursor was displayed. An input of "H" data enables the underline display, while an input of "L" data deletes the underline. 8. Character Generator ROM (CG ROM) CG ROM stores the character pattern. MSM6262-XX has 128 kinds of 5 x 7-dot patterns, 96 kinds of 5 x 11-dot patterns and 32 kinds of 5 x 12-dot patterns. The character pattern corresponds to the character code which is written into the DD RAM. The relation between 8-bit character code and character pattern is described in Table 1. When the 8-bit character code of CG ROM is written into the DD RAM, the character pattern of the corresponding character code of the CG ROM is displayed on the LCD position corresponding to the DD RAM address. When all of the upper 4 bits of CG ROM code are "L", CG ROM can be switched to CG RAM.
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Semiconductor
MSM6262-XX
Table 1 Character code and character pattern of Standard Code (MSM6262-04)
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Semiconductor 9. Character Generator RAM (CG RAM)
MSM6262-XX
The CG RAM is used to display user's original character pattern other than CG ROM. The CG RAM has capacity (32 bytes = 256 bits) to write 4 kinds of 5 x 8 dots and 2 kinds of 5 x 12 dots. In displaying the character pattern stored in the CG RAM, CG RAM has to be enabled by an instruction. When CG RAM is enabled, CG ROM code for 16 characters cannot be read out since the CGROM code with all "L" on the upper 4 bits is used as CG RAM code. The following describes how to write character patterns into the CG RAM and how to display them on the LCD. (1) When the character pattern is 5 x 8 dots (See Table 2-1) * A method to write character pattern into the CG RAM by the CPU The lower 3 bits (0 - 2) of the CG RAM address correspond to the line position of the character pattern. The upper 2 bits (3, 4) of the CG RAM address correspond to the lower 2 bits (0, 1) of the character code. First, set increment of decrement by the CPU, and then input CG RAM address. After this, write character pattern data into CG RAM through DB0 to DB7 line by line. DB0 - DB7 correspond to CG RAM data 0 - 7 in Table 2-1. Display is turned on when "H" is set as input data and turned off when "L" is set as input data. Since the ADC is automatically incremented or decremented by 1 after the writing of data to the CG RAM, it is not necessary to set the CG RAM address again. To enable cursor display, set all input data on the line where the lower 3 bits of the CG RAM (0-2) are all "H" to "L". 0 - 4 bits of CG RAM data are output to the LCD as the display data; however, 5 - 7 bits of CG RAM data are not. But it can be used as the data RAM because the data can be written/ read through DB0 to DB7. * A method to display the CG RAM character pattern to the LCD First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is selected only when all of the upper 4 bits of the character code is "L". So, the character pattern of CG RAM is displayed on the LCD position that corresponds to the DD RAM address, when the character code shown in Table 2-1 is written into DD RAM. Since the bits 2 and 3 of the character code are regarded as invalid, "K" is displayed when the character codes "01", "05", "'09", and "0D" are selected. (2) When the character pattern is 5 x 12 dots (See Table 2-2) * A method to write character pattern into the CG RAM by the CPU The lower 4 bits of CG RAM address (0 - 3) correspond to the line position of the character pattern. The upper 1 bit of CG RAM address bit 4 corresponds to the bit 1 of the character code. First, set increment or decrement by the CPU, and then input CG RAM address. After this, write the character pattern data into CG RAM through DB0 to DB7 line by line. DB0 - DB7 correspond to CG RAM data 0 - 7 in Table 2-2. Display is turned on when "H" is set as the input data and turned off when "L" is set 25/52
Semiconductor
MSM6262-XX
as the input data. Since the ADC is automatically incremented or decremented by 1 after the writing of data to the CG RAM, it is not necessary to set the CG RAM address again. To enable cursor display, set all input data on the line where the CG RAM address is "0B" or "1B" (hex.) to "L". The addresses "0" to "B" (hexadecimal) in the bits 0 to 4 of the CG RAM data are output on the LCD as the display data. However, the addresses "C" to "F" (hexadecimal) in the bits 0 to 4, and 5 to 7 of the CG RAM data are not output on the LCD. But these CG RAM data can be used as the data RAM so that they can be written into or read out through DB0 to DB7. * A method to display the CG RAM character pattern on the LCD First, an instruction to enable the CG RAM has to be input from the CPU. CG RAM is selected only when all of the upper 4 bits of the character code is "L". So, the character pattern of CG RAM is displayed on the LCD position corresponding to the DD RAM address, when the character code shown in Table 2-2 is written into the DD RAM. Since bits 0, 2 and 3 of the character code are regarded as invalid, the character of "m" is displayed when the character codes "00", "01", "04", "05", "08", "09", "0C" and "0D" are selected. (3) A method to read out the CG RAM data First, set the CG RAM address by inputting a CG RAM address set instruction from the CPU. Then, execute the CG RAM/DD RAM data read instruction. The set data of CG RAM address is output from the DB0 to DB7. The 8-bit data, read out from the MSM6262-XX, corresponds to the data which is written into the CG RAM. Since the CG RAM address is automatically incremented or decremented by 1, the CG RAM read out instruction c a n be successfully input. It is necessary, however, to set the DD RAM at data transferring condition by executing the DD RAM address set instruction after all of CG RAM data are read out.
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Semiconductor
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Table 2-1 Relation between CG RAM data (character pattern) vs. CGRAM address and DDRAM data vs. character pattern when the character pattern is 5 8 dots.
CG RAM ADDRESS CG RAM DATA (Character Pattern ) DD RAM DATA (Character Code )
43210 76543210 76543210 LSB MSB LSB MSB LSB LLLLL XXXLHHHL HLLLH LLH HLLLH LHL LHH HLLLH LLLLXXLL HLLLH HLL HLLLH HLH L HHHL HHL LLLLL HHH LHL L L L H H H H L L H H L L H H L H L H L H L H XXXH H H H H H H L L L L H L L L L L L H L H L L L L H L L L H L L H L L L L L H L
LLLLXXLH
HHL L L L H H H H
L L H H L L H H
L H L H L H L H
XXXL L L L L L L L
H L L L L L H L
H H H H H H H L
H L L L L L H L
L L L L L L L L
LLLLXXHH
X: Don't care
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Semiconductor
MSM6262-XX
Table 2-2 Relation between CGRAM data (character pattern) vs. CGRAM address and DDRAM data vs. character pattern when the character pattern is 5 12 dots.
CG RAM CG RAM DATA DD RAM DATA (Character Code) ADDRESS (Character Pattern) 43210 76543210 76543210 LSB MSB LSB MSB LSB LLLL XXXLLLLL L LLLLL LLLH LLLLL LLHL LLHH L HLLL L HHHH LHLL HLLHL LHLH LLLLXXLX LHHL L HHHH LHHH L HLHL HLLL HHHHH HLLH L LLHL HLHL LLLLL HLHH LLLLL XXXXX HHLL HHLH HHHL HHHH HLLLL XXXLLLLL LLLLL LLLH LLLLL LLHL LLHH LLLLL LLLLL LHLL HLLLH LHLH LLLLXXHX HLLLH LHHL L HLHL LHHH HLLL LLHLL HLLH L HLLL HLHL HLLLL HLHH LLLLL HHLL XXXXX HHLH HHHL HHHH X: Don't care
B
B
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Semiconductor
MSM6262-XX
9. LCD Display Circuit (COM1 to COM48, DO, CP, LOAD, DF) The MSM6262-XX is provided with COMMON signal output. So, maximum 160 characters can be displayed when it is used together with SEGMENT drivers (MSM5259 or MSM5839C). Interface between MSM6262-XX and SEGMENT drivers can be done by using DO, CP, LOAD and DF. The SEGMENT data is serially output from DO pin, synchronized with the pulse which is output from the CP pin. This data, input to the SEGMENT driver, is converted from serial data to parallel data by the latch pulse which is output from the LOAD pin of MSM6262-XX and this converted data is used as the display data. This parallel/serial conversion is performed synchronized with the COMMON signal of MSM6262-XX and LCD display AC signal which is output from DF pin. So, this signal can drive dot matrix LCD panel. 10. Reset Circuit Power-on-reset is required for MSM6262-XX when it is powered-on. So, a capacitor has to be connected between RESET pin and VSS pin. It is also advisable to connect a diode between RESET pin and VDD pin when it is required to connect a capacitor of more than 3.3 F to RESET pin. When the power-on reset circuit normally operates, the busy flags 1 and 2 become at "H" level for about 10 ms after the power-on. During this period, a initialization of MSM6262-XX is performed by following procedures. 1 Display is cleared 2 CG ROM becomes enabled 3 No display shift 4 ADC is incremented 5 2-line display mode 6 5 x 8 dots font configuration 7 No display shift for "g", "j", "p", "q" and "y" 8 Display off 9 No display of cursor, blinking and underline 11. Data Bus with CPU MSM6262-XX can be interfaced with 8-bit CPU, such as 6809, Z80, 80C49 and 80C51. When MSM6262-XX is connected with 6809, the 68 series/80 series pin has to be connected to VDD. When MSM6262-XX is connected with Z80, 80C49 or 80C51, the 68 series/80 series pin has to be connected to VSS. The level at 68 series/80 series cannot be switched during MSM6262-XX's operation. It must be connected with either VDD or VSS before MSM6262-XX is turned on. Note: It is possible, indeed, to change the 68 series/ 80 series pin's level when a reset signal is being input to RESET pin. However, the 68 series /80 series pin does not have characteristics to have an interface with MCU, nor does it have an antichattering circuit. Further, if a reset signal is input, the MSM6262-XX is initialized as described above. So, in this case, changing the 68 series/80 series pin level is not recommended.
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Semiconductor
MSM6262-XX
E (RD)
R/W (WR) A1 A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BUSY1 (Internal operation) BUSY2 (Internal operation)
, ,, ,, , ,, ,, ,
80 series CPU data transfer
NO BUSY1 NO BUSY2 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 BUSY1 BUSY2 * * * * * * DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
CG/DD
I/D S
A/O D
UD
Write an instruction (IR)
Read the busy flag
Write the data register (RD)
* : Don't care
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Semiconductor
MSM6262-XX
68 series CPU data transfer
,, ,, , , , , ,, , , ,
E (RD) R/W (WR) A1 A0 NO BUSY1 NO BUSY2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 BUSY1 BUSY2 * * * * * * DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
CG/DD
I/D S
A/O D
UD
BUSY1 (Internal operation) BUSY2 (Internal operation)
Write an instruction (IR) * : Don't care
Read the busy flag
Write the data register (RD)
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Semiconductor
MSM6262-XX
Instruction Table
* : DON'T CARE
80series CPU Note 68se 1 ries CPU R/W L Display Clear
A1 A1 L L L
A0 A0 L L L
DB7 DB7 L L L
DB6 DB6 L L L
DB5 DB5 L L L
DB4 DB4 L L L
DB3 DB3 L L L
DB2 DB2 L L H
DB1 DB1 L H UL
DB0 DB0 H CR/C *
Explanation
Clears all of the display. and sets address 0 of DD RAM in the address counter. CR/C = L: Cursor home CR/C = H: Carriage Return UL = H: Writes the underline in the cursor part before executing this instruction. UL = L : Erases the underline in the cursor part before executing this instruction. Sets whether the display of the direction of cursor (I/D) move should be shifted or not. When the data is being written or read, this operation is performed. This instruction also sets whether the character code of DD RAM is used as CG ROM or CG RAM.(A/O) Shifts the cursor and display without changing the DD RAM contents. (S/C, UD/RL,UR/DL) The line to be displayed in the uppermost position can be set. Sets the CG RAM address. The dara, which will be sent/received after the CG RAM address is set, is CG RAM data. Sets the following: No. of display digits (N), Character font (F1), Cursor line font (F2), Font shift of "g, j, p, q, y" (F3) Sets the following: All display on/off (D), Cursor display on/off (C), Character on the cursor position blink on/off (B), Underline display on/off (UC), Character, on the underline, blink on/off (UB) Writes a data in either DD RAM or CG RAM. Sets DD RAM address. The data which is sent/received after that is DD RAM data. Reads following data: Data on the underline, DD RAM or CG from RAM data. Reads the data either from DD RAM or from CG RAM. Reads the address counter contents.
Busy 1 flag (B1F) shows that MSM6262-XX's internal operation is going on. Busy 2 flag (B2F) shows that the revising of display starting line is going on. CG/DD shows whether the data, being transmitted or received, is of CG RAM or DD RAM. I/D shows the direction in which cursor moves. S shows the display shift. A/O shows that the DD RAM character code is CG RAM character code or CG RAM character code. D shows the all display on/off. UD shows underline display on/off. DD RAM : Display data RAM CG RAM : Character generator RAM ACG : CG RAM address ADD : DD RAM address ADC : Address counter which is used for both DD RAM and CG RAM
Execution Time (MAX), When fosc = 500kHz
3.22 ms 1.62 ms
Return Under Line
L L
20 ms
Entry Mode Set
L
L
L
L
L
L
L
H
I/D
S
A/O
20 ms
Display/Cursor Shift
L
L
L
L
L
L
H
S/C
UD/ RL
()
D2 UR/ DL
D1 () *
20 ms
CG RAM address Set
L
L
L
L
L
H ACG
20 ms
Function Set
L
L
L
L
H
N
*
F1
F2
F3
*
20 ms
Display Control
L
L
L
H
D
C
B
UC
UB
*
*
20 ms
CG RAM/DD RAM Data Write DD RAM Address Set Read the Underlined Data Read the CG RAM/ DD RAM Data Read the Address Counter Content Read Busy Flag
L L H H H H
L H L L H H
H L L H L H B1F B2F CG/ DD ULD
WRITE DATA ADD READ DATA READ DATA ADC I/D S A/O D UD
20 ms 20 ms 20 ms 20 ms 0 ms
0 ms
CR/C = H : : UL = H : I/D = H : S=H A/O = L : S/C = H : UD/RL = H : : D2,D1 UR/DL = H : : N =L : N =H : F1 = H : F2 = L : F3 = H ULD = H B1F = H B2F = H : : :
CG/DD = H :
Carriage Return CR/C = L : Cursor home Write underline : Underline erase UL = L Increment : Decrement I/D = L Accompany display shift CG ROM ENABLE A/O = H : CG RAM ENABLE Display move S/C = L : Cursor move Up/Down move UD/RL = L : Left/Right move The bit to set the line to be displayed in the uppermost position. : D1 is LSB. D2 is MSB. Upper-right move UR/DL = L : Down-left move 2 lines 4 lines : 5 x 7 dots 5 x 11 dots F1 = L : 5 x 11 dots or 5 x 7 dots F2 = H 5 x 12 dots or 5 x 8 dots : Disable character shift F3 = L Shift "g, j, p, q, y" to the lower position by 1 dot. ULD = L : No underline data Underline data exists B1F = L : Ready to receive instruction Internal operation going on B2F = L : No revision on display Revising the display starting starting line line or internal operation going on CG/DD = L : Transmit/Receive of DD RAM data Transmit /Receive CG RAM data
When fosc = 600 kHz, execution time becomes 500 20 ms---- 600
** 16.7 ms =
Note 1: In the case of 80 series CPU, access to MSM6262-XX is done by WR and RD. So, a bit for part of the read/write code is not required.
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Semiconductor 12. Instruction Code
MSM6262-XX
The instruction code is defined as the signal through which the MSM6262-XX is accessed by the CPU. MSM6262-XX starts its operation upon receipt of the instruction code. The internal processing operation starts with a timing that does not affect the LCD display, so, the busy condition is longer than that of cycle time. In the busy condition, MSM6262-XX does not execute any instruction other than the reading of busy flag. Therefore, make certain that busy flag is set at "L" before inputting the instruction code. (1) Display clear
A1 Instruction code L A0 L DB7 L DB6 L DB5 L DB4 L DB3 L DB2 L DB1 L DB0 H
When this instruction is executed, the LCD display is cleared. When cursor display and/or character blink is being performed, their display position moves to the left end of the LCD. (In the case of 2-line or 4-line display mode, it moves to the left end of the first line.) All of the DD RAM data becomes "20" (hex), while ADC data becomes "00" (hex.). If the display is on a shifted position, it returns to the original position. Data for underline is re-written as "L" and display turns off. (2) Return * CR/C = L (Cursor home)
A1 Instruction code L A0 L DB7 L DB6 L DB5 L DB4 L DB3 L DB2 L DB1 H DB0 CR/C
When this instruction is executed, cursor and blinking position moves to the left end of the LCD. (In the case of 2-line or 4-line display mode, it moves to the left end of the first line.) When display is being shifted, the display returns to its original position for both horizontally and vertically. ADC becomes "00" (hex.). * CR/C = H (Carriage return) When this instruction is executed, cursor and blinking position moves to the left end of the line on which the cursor and brink were positioned before execution of instruction. If the display is being shifted when this instruction was executed, the cursor and blinking position moves to the original position before it was shifted only concerning to the shift to the right and left. All bits other than line specifying bit of ADC will be reset to "0" (hex.).
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(3) Underline
A1 Instruction code L A0 L DB7 L DB6 L DB5 L DB4 L DB3 L DB2 H DB1 UL DB0 *
*: Don't care
* UL = H (Write underline) When this instruction is executed, the underline appears on the cursor position. Cursor will move to the right or left if either increment or decrement is specified. * UL = L (Erase underline) When this instruction is executed, the underline on the cursor position disappears. Cursor will move to the right or left if either increment or decrement is specified. When this instruction is executed, ADC will be automatically incremented by +1 or decremented by -1. Display is shifted accordingly. (4) Entry mode set
A1 Instruction code L A0 L DB7 L DB6 L DB5 L DB4 L DB3 H DB2 I/D DB1 S DB0 A/O
* I/D (Increment/Decrement) When this instruction is executed, DD RAM address will be incremented (I/D = "H") or decremented (I/D = "L") by 1, after the character code or underline code is written into (or read out from) the DD RAM. In the case of increment, cursor moves to the right, while the cursor moves to the left in the case of decrement. Processing for writing/reading the data into/from CG RAM is performed the same way. * S (Display shift upon writing) When S = "H" and data is written into DD RAM, display is shifted either to the right or left. When I/D = "H", the whole display shifts to the left, while it shifts to the right when I/D = "L". So, display of cursor looks being stopped and display itself looks being shifted. In the case of reading the data from DD RAM, display is not shifted. Also in the case of reading/writing the data from/to CG RAM, display shall not be shifted. When S = "L", display is not be shifted. * A/O (CG RAM ENABLE/CG ROM ENABLE) When A/O is "L", CG ROM will be enabled, and all CG ROM contets on Table 2 becomes selectable and CG RAM cannot be selected. CG RAM cannot be used as character code for display. But it can be used as data RAM. When A/O = "H", CG RAM is enabled. When the upper 4 bits of the character code in Table 1 are "00" (hex.), the bit pattern of CG RAM is displayed on the LCD. (CG RAM has a RAM area for 4 kinds of 5 x 8 dots and 2 kinds of 5 x 12 dots) CG ROM is selected when the upper 4 bits of the character code in Table 1 are "01" - "0F" (hex.).
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Semiconductor
MSM6262-XX
(5) Display/Cursor move
A1 Instruction code L A0 L DB7 L DB6 L DB5 L DB4 H DB3 S/C DB2 UD/ RL DB1
D2 (UR/ DL)
DB0 D1 (*)
*: Don't care
* S/C (Display move/Cursor move) This is the bit to select either display or cursor to move. S/C = "H" enables the display movement, while S/C = "L" enables the cursor movement. * UD/RL (Upward or downward move/Right or left move) UD/RL = "H" enables upward or downward move. UD/RL = "L" enables right or left move. * D2, D1 (Starting line of display) Upward or downward movement is enabled by setting the starting line of display. D1 is LSB and D2 is MSB. Both D1 and D2 are expressed in 2-bit binary data. Only D1 is valid in 2-line mode. Both D1 and D2 are valid in 4-line mode.
[ 2-line mode ] DD RAM 1st line 2nd line D2 = *, D1 = "L" Display of the LCD 1st line 2nd line
D2 = *, D1 = "H" 1st line 2nd line 1st line 2nd line
* : Don't care
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Semiconductor
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[ 4-line mode ] DD RAM 1st line 2nd line 3rd line 4th line D2 = "L", D1 = "H" 1st line 2nd line 3rd line 4th line D2 = "H", D1 = "L" 1st line 2nd line 3rd line 4th line D2 = "H", D1 = "H" 1st line 2nd line 3rd line 4th line 1st line 2nd line 3rd line 4th line 1st line 2nd line 3rd line 4th line 1st line 2nd line 3rd line 4th line D2 = "L", D1 = "L" Display of the LCD 1st line 2nd line 3rd line 4th line
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Semiconductor
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* UR/DL (Up-right move/Down-left move) UR/DL = "H" enables up-right movement. UR/DL = "L" enables down-left movement. Combination of bit for Display/Cursor movement is as follwes
S/C L L L L H H H H H H
UD/ RL L L H H L L H H H H
D2 (UR/ DR)
D1 * * * * * * * L H L H
Explanation Move the cursor to the left by 1 digit Move the cursor to the right by 1 digit Move the cursor downward by 1 digit Move the cursor upward by 1 digit Move the display to the left by 1 digit Move the display to the right by 1 digit Set the first line as the display starting line Set the 2nd line as the display starting line Set the 3rd line as the display starting line s Set the 4th line as the display starting line s
L H L H L H L L H H
* : Don't care
s : Invalid in 2-line mode
(6) CG RAM address set
Instruction code A1 L A0 L DB7 L DB6 L DB5 H DB4 Ac4 DB3 Ac3 DB2 Ac2 DB1 DB0 Ac1 Ac0
Set the CG RAM address which consists of 5 bits of Ac4 - Ac0. The data which will be transferred after this instruction is set will be limited to the CG RAM data (character font data).
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Semiconductor
MSM6262-XX
(7) Function set
A1 L A0 L DB7 L DB6 H DB5 N DB4 * DB3 F1 DB2 F2 DB1 DB0 * F3
Instruction code
*: Don't care
* N (Selection of LCD lines to be displayed)
N L H LCD lines 2-line mode 4-line mode
* F1 (5 x 11 dots/5 x 7 dots) When F1 = "H", 5 x 12-dot font is selected. When F1 = "L", 5 x 8-dot font is selected. * F2 (Font assignment of cursor line) When F2 = "L" and if character code, which has a display dot on the cursor position, is selected, it is displayed on the cursor line of LCD. When F2 = "H" and if character code, which has a display dot on the cursor position, is selected, cursor is displayed but the bit on the cursor position is not displayed. However, this function does not apply to CG RAM and the bit on the cursor position is also displayed. * F3 (Character shift of "g, j, p, q, y") When F3 = "H", each character of "g, j, p, q, y" is displayed shifted downward by 1 dot for the whole character. When F3 = "L", display of these characters is the same as other characters, as shown in Table 1. This bit is valid only for 5 x 12-dot font. Example
q F1 = "L" (5 x 8-dot/font)
5 x 11- or 5 x 12-dot font ROM 5 x 7-dot font ROM 3 dots 7 dots Cursor position Cursor Not displayed
1 or 2 dots
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Semiconductor
MSM6262-XX
w
F1 = "H" (5 x 12-dot/font)
5 x 7-dot font ROM 3 dots 7 dots
(1 dot)
5 x 11-dot font ROM
5 x 12-dot font ROM
Cursor position
1 dot
e
F2 = "H"
r
F2 = "L"
Cursor position
t
F3 = "L"
y
F3 = "H" (5 x 12-dot font only)
Cursor position
Shifted downward by 1 dot
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Semiconductor (8) Display control
A1 Instruction code L A0 L DB7 H DB6 D DB5 C DB4 B DB3 UC DB2 UB DB1 * DB0 *
MSM6262-XX
*: Don't care
* D (All display on/off) When D = "H", display on the LCD is enabled. When D = "L", display is disabled. When display was disabled by setting D at "L", character code in the DD RAM does not change. So, when D becomes "H" again, display is enabled immediately. * C (Cursor display on/off) C = "H", cursor display appears. When C = "L", cursor display disappears. * B (Cursor blinking) When B = "H", blinking of character on the position corresponding to the cursor position, starts. Blinking of all-dot's-on and character (and cursor)-on is performed alternately for every 409.6 ms in case of fosc = 500 kHz and 5 x 8 dots font configuration (every 614.4 ms in case of 5 x 12 dots font configuration) When B = "L", blinking stops. Cursor and blinking can be set together. * UC (Underline display) When UC = "H", underline is displayed on the cursor position. When UC = "L", underline display is disabled. * UB (Underlined character blinking) When UB = "H", blinking of character on the position corresponding to the underline position, starts. Blinking of character stops when UB = "L". Cursor, blink, underline, and blinking of character on the underline can be set together. (9) CG RAM and DD RAM data write
A1 Instruction code L
A0 H
DB7 DI7
DB6 DI6
DB5 DI5
DB4 DI4
DB3 DI3
DB2 DI2
DB1 DI1
DB0 DI0
Write the 8-bit data (DI7 - DI0) into either CG RAM or DD RAM. Determination of either CG RAM or DD RAM is made by the previously set CC RAM or DD RAM address set. After the data is written into the RAM, it is incremented or decremented by 1 according to the entry mode of the address. Display shift is also determined by the entry mode.
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Semiconductor (10) DD RAM address set
A1 Instruction code H A0 L DB7 AI7 DB6 AI6 DB5 AI5 DB4 AI4 DB3 AI3 DB2 AI2 DB1 AI1 DB0 AI0
MSM6262-XX
This instruction code sets the DD RAM address, which consists of 8 bits (AI7 to AI0). The data which is received after this instruction is set is limited to the DD RAM data (character code data). Do not input any address code other than those below. 2-line mode : 1st line 00 - 4F 2nd line 80 - CF 4-line mode : 1st line 00 - 27 2nd line 40 - 67 3rd line 80 - A7 4th line C0 - E7 (11) Underline data read
A1 Instruction code L A0 L DB7 ULD DB6 D06 DB5 D05 DB4 D04 DB3 D03 DB2 D02 DB1 D01 DB0 D00
This instruction reads underline data, and CG RAM or DD RAM data. Determination of CG RAM or DD RAM is made by the previously set CG RAM or DD RAM address set. The first data read by this instruction is an invalied data. Normal data is read out from the second instruction onward if the read instruction is executed continuously. This instruction address will be incremented or decremented by 1 according to the entry mode. Display shift is, however, not performed. Underline data is output to DB7 as either "H" (when display is on) or "L" (when display is off). The MSB of RAM data is not read. RAM data consists of 7 bits (DB0 to DB6).
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Semiconductor (12) CG RAM and DD RAM data read
A1 Instruction code L A0 H DB7 D07 DB6 D06 DB5 D05 DB4 D04 DB3 D03 DB2 D02 DB1 D01 DB0 D00
MSM6262-XX
This instruction reads the 8-bit data (DO7 to DO0) from either CG RAM or DD RAM. Determination of CG RAM or DD RAM is made by the previously set CG RAM or DD RAM address set. The CG RAM address set instruction or DD RAM address set instruction has to be input just before executing this read instruction. If it is not input, the first output of the data becomes invalid. When this read instruction is performed continuously, normal data is output from the 2nd data onward. In the case of DD RAM data read, normal data is output from the first data even if the address set is not input, provided that cursor is moved by the cursor shift instruction. After reading the data, the address is incremented or decremented by 1 by the entry mode. The shift of the display, however, is not performed. (13) Address counter read
A1 Instruction code H A0 L DB7 A07 DB6 A06 DB5 A05 DB4 A04 DB3 A03 DB2 A02 DB1 A01 DB0 A00
This instruction reads the 8-bit data (AO7 to AO0) . Address counter is determined by the previously set address set because it is used for both CG RAM and DD RAM. (14) Busy flag read
A1 Instruction code H A0 H DB7 B1F DB6 B2F DB5 CG/ DD DB4 I/D DB3 S DB2 A/O DB1 D DB0 UD
*
*
B1F (Busy 1 flag) When B1F = "H", MSM6262-XX is engaged in internal operation and next instruction is not accepted until when B1F becomes "L". So, subsequent instruction has to be input after B1F is confirmed at "L". During B1F = "H", DB5 to DB0 are undefined. B2F (Busy 2 flag) B2F indicates that MSM6262-XX is engaged in its internal operation and it also indicates that the display starting line is under being revised. Instruction contents of B1F and B2F are the same except when setting the starting line of display. B2F = "H" indicates that MSM6262-XX is engaged in its internal operation. B2F = "L" indicates that MAM6262-xx is ready for accepting new instruction. Even when B2F = "H", new instruction can be accepted if B1F = "L". However, if the starting line of display is revised under this condition, the previous set data about starting line of display becomes invalid and the newly input data about starting line becomes valid.
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Semiconductor
MSM6262-XX
* CG/DD (CG RAM/DD RAM) This bit indicates whether the address counter contents are CG RAM or DD RAM when B1F = "L". It indicates that CG RAM data has been selected when CG/DD = "H" and that DD RAM data has been selected when CG/DD = "L". * I/D (Increment/Decrement) This bit indicates which has been set in the entry mode set, increment or decrement, when B1F = "L". It indicates that increment has been set when I/D = "H" and that decrement has been set when I/D = "L". * S (Shift) This bit reads the shift condition in the entry mode when B1F = "L". It indicates that shift is set when S = "H" and shift is disabled when S = "L". * A/O (CG RAM ENABLE/CG ROM ENABLE) This bit indicates which has been selected in the entry mode, CG ROM or CG RAM, when BIF = "L". It indicates the CG ROM selected state when A/O = "L" and CG RAM selected state when A/O = "H". * D (Display) This bit indicates which has been set by display control instruction, LCD display ON or OFF, when B1F = "L". It indicates that the display is on when D = "H" and the display is off when D = "L". * UD (Underline) This is the bit to indicate the condition of underline or blinking on the underline, both of which were set by display control instruction, when B1F = "L". When UD = "H", either (or both of) underline display or blinking on the underline is being executed. When UD = "L", it indicates neither of underline display nor blinking on the underline is performed.
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Semiconductor
MSM6262-XX
APPLICATION CIRCUITS
1 2-line display mode 5 x 7 dots, 2 lines 16 characters (Note: COM17 - COM48 should be left open) COM1
COM16 COM17 COM48 MSM6262-XX DO DF CP LOAD
LCD
O1 DI1 O40 DO40 O1 DI1 O40 MSM5259 CP LOAD DF DO20 DI21 MSM5259 CP LOAD DF DO20 DI21
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2
2-line display mode 5 x 11 dots, 2 lines 16 characters (Note: COM25 - COM48 should be left open)
COM1
underline
COM24 COM25 COM48 MSM6262-XX DO DF CP LOAD O1 DI1 O40 DO40
LCD
cursor O1 DI1 O40
MSM5259 CP LOAD DF DO20 DI21
MSM5259 CP LOAD DF DO20 DI21
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3
4-line display mode 5 x 7 dots, 4 lines 16 characters (Note: COM33 - COM48 should be left open)
LCD
COM1
COM32 COM33 COM48 MSM6262-XX DO DF CP LOAD
O1 DI1
MSM5839C CP LOAD DF DO20 DI21
O40 DO40
O1 DI1
O40
MSM5839C CP LOAD DF DO20 DI21
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Semiconductor
MSM6262-XX
4
4-line display mode 5 x 11 dots, 4 lines 16 characters
LCD
COM1
COM48 MSM6262-XX DO DF CP LOAD O1 DI1 O40 DO40 O1 DI1 O40
MSM5839C CP LOAD DF DO20 DI21
MSM5839C CP LOAD DF DO20 DI21
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*
MSM6262-XX COM1 LCD COM48
Semiconductor
DO DO40 MSM5839C CP DO20 LOAD DI21 DF VDD VSS V2 V3VEE DO40 MSM5839C CP DO20 LOAD DI21 DF VDD VSS V2 V3VEE V2V3 VEE
DI1
O1 ~ O40 DI1 DI1
O1 ~ O40
DO40 MSM5839C CP DO20 LOAD DI21 DF VDD VSS V2 V3VEE
O1 ~ O40
CP LOAD DF VDD VSS V1
Example of connection with MSM5839C and bias circuit
V4 V5 C C C C C C
R 5V
R
4R C
R
R
VR
r -5 V
0V
MSM6262-XX
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*
Example of bias circuit
1/5 - 1/8 bias example 1. Bias RR 1/5 R 1/6 2R 1/7 3R 1/8 4R
VLCD: LCD driving voltage VDD R V1 R MSM6262-XX V2 RR V3 R V4 R V5 r VR VEE to segment driver VLCD
1/5 - 1/8 bias example 2. Bias RR 1/5 R 1/6 2R 1/7 3R 1/8 4R
VLCD: LCD driving voltage
VDD CR V1 R MSM6262-XX C C RR R R r VR C C VEE C V3 V4 V5 to segment driver VLCD C V2
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MSM6262-XX
*
LCD duty and bias
No. of lines Duty Bias
2 lines 1/16 1/5 1/24 1/6
4 lines 1/32 1/7 1/48 1/8
Above are examples of relation between LCD duty and bias. Use these values for reference, for they vary depending on the characteristics of LCD panel. The value of resistor on bias circuit is determined by the operational margin and power consumption. To make the power consumption lower, the value of resistor has to be larger, but it makes the LCD driving output impedance high and causes the distortion on the LCD driving waveform. If a large LCD panel is used, the value of the resistor should be much lower because the LCD capacitance increases. Connecting a bypass capacitor to the bias resistor in parallel can improve the distortion of LCD driving waveform. However, connecting a capacitor of too large value may cause a level shift of the bias voltage. So, it has to be determined carefully after checking experimentally. Followings are the reference values. R = 2 to 10 kW VR = 10 to 50 kW r = 0.2 to 2 kW C = 0.0022 to 0.047 mF
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*
LCD driving waveform (at 1/5 to 1/8 bias)
12 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5
12
12
COM1
COM2
Lighting waveform VDD V1 V2 V3 V4 V5
SEG
DF 1 frame
Duty Frame frequency Note: fosc = 500 kHz
1/16 78.125 Hz
1/24 52.08 Hz
1/32 78.125 Hz
1/48 52.08 Hz
Selecting a SEGMENT driver IC When VLCD is within the voltage range of VDD and that of VSS, MSM5259 is recommendable as SEGMENT driver. When VLCD is beyond the voltage range of VDD and that of VSS, MSM5839C or MSM5260 is recommendable as SEGMENT driver.
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Semiconductor
MSM6262-XX
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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